Hybrid memory system and spin-buffer journaling in a gaming machine

ABSTRACT

A gaming machine is comprised of a processor, an interface, and a hybrid non-volatile memory component having a byte-addressable non-volatile memory sub-component and a block-addressable non-volatile memory sub-component. The machine is capable of storing critical gaming data or data that is required to be stored pursuant to gaming regulations in an efficient, reliable, and cost-effective manner. The byte-addressable sub-component (the “expensive” memory) has at least three buffers for temporarily storing critical game data and the block-addressable sub-component (the “lower cost” memory) has at least one block for storing game data, wherein critical gaming data is transferred from the byte-addressable sub-component to the block-addressable sub-component, where it is permanently stored. The block-addressable memory may be flash memory. A confirmation is sent from the block-addressable sub-component to the byte-addressable sub-component when the critical gaming data is permanently stored. The critical gaming data is deleted from the byte-addressable sub-component when the confirmation is received. In one embodiment, the byte-addressable sub-component is a memory that continues to store data during a power loss, in contrast to the block-addressable memory, which may lose data during a write operation if a disruption occurs.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to wager gaming machines and memorymanagement. More specifically, it relates to managing gaming machinedata using two types of memory and a spin buffering methodology.

2. Description of the Related Art

In a gaming machine network, slow-speed serial lines have kept theamount of data that could be transmitted in the network relativelysmall. Gaming control board regulations and casino policies were limitedby what the technology could provide. For example, increments in metersand a few bytes indicating an action, such as a wheel spin, was all thatwas typically sent over the network. This required a few bytes of dataand was suitable for transmission over serial lines.

When Ethernet was introduced, the speed with which data could betransmitted increased by orders of magnitude. For example, programmerscould now wrap data in XML and use other similar techniques. With theintroduction of Ethernet, much larger amounts of data could betransmitted and at much faster speeds. Gaming regulatory bodies thenrequired that more data be stored. For example, with Ethernet, 512 bytepackets for each event on a gaming machine could now be sent. However,with these new requirements and speed came the significantly increasedneed for extra storage capacity on a gaming machine. As is known in theart, a gaming machine logs data on the machine and stores the data, forexample, in a CMOS nvRAM on the machine. This type of battery-backednon-volatile memory is expensive and now reaches capacity very quicklywith the new requirements for storing data for each event, which may beany type of gaming transaction or any synchronous or asynchronous gamingmachine event. Gaming machines use nvRAM primarily because of its writespeed. Hard drives are typically too slow.

The capacity of non-volatile memory on older gaming machines was, forexample, in the 128k range. But what is now needed is more in the rangeof 16 MB of such memory. The newest AVP i960 gaming machine from IGT,Inc. of Reno, Nev., does not have enough nvRAM now that some gamingcontrol boards are requiring that complete pictures of all the metersand other data be stored by the gaming operator, even if such storagemay be on the machine or at another memory source, for example, a serverin the gaming network. In another example, in a server-based gamingenvironment using new protocols that take advantage of Ethernet (e.g.,G2S, developed in part by IGT), storage of large amounts of data isneeded for game and system log data.

SUMMARY OF THE INVENTION

In one embodiment, a gaming machine is comprised of a processor, aninterface, and a hybrid non-volatile memory component having abyte-addressable non-volatile memory sub-component and ablock-addressable non-volatile memory sub-component. Thebyte-addressable sub-component has at least three buffers fortemporarily storing critical game data and the block-addressablesub-component has at least one block for storing game data, whereincritical gaming data is transferred from the byte-addressablesub-component to the block-addressable sub-component, where it ispermanently stored. A confirmation is sent from the block-addressablesub-component to the byte-addressable sub-component when the criticalgaming data is permanently stored. The critical gaming data is deletedfrom the byte-addressable sub-component when the confirmation isreceived. In one embodiment, the byte-addressable sub-component is amemory that continues to store data during a power is loss, in contrastto the block-addressable memory, such as flash memory, which may losedata during a write operation if a disruption occurs.

In another embodiment, a method of storing gaming data in a hybridmemory component in a gaming machine is described, where the gaming datais required to be stored is dictated by relevant gaming regulations. Thegaming data is received at the hybrid memory component from one or morecomponents in the gaming machine. It is then determined if abyte-addressable non-volatile memory buffer in the hybrid memorycomponent is at maximum storage capacity with the required gaming data.If the buffer is at maximum storage capacity, the gaming data from thebuffer is written to a block in the block-addressable non-volatilememory, while the gaming data continues to be stored in the bufferduring the writing. If it is not at maximum storage capacity, the buffercontinues to receive gaming data from the one or more components. If thewriting operation is complete, at the block-addressable non-volatilememory, it is checked if the gaming data has been stored persistently.If the gaming data has been stored persistently in the block-addressablenon-volatile memory, a confirmation is sent from the block-addressablenon-volatile memory to the byte-addressable non-volatile memory buffer.The gaming data is deleted from the buffer when the confirmation isreceived, thereby freeing the buffer to receive new data, such thatgaming data is not lost if there is a disruption during the writingoperation.

In one embodiment, a gaming device capable of storing required gamingdata pursuant to wager gaming regulations is described. The deviceincludes a master gaming controller, a hybrid non-volatile memorycomponent having a byte-addressable memory, a block-addressable memory,an FPGA, and a memory. The memory stores computer instructions forperforming various operations on the gaming device. In one embodiment,the required gaming data is received at the hybrid memory component fromthe master gaming controller. It is then determined if abyte-addressable non-volatile memory buffer in the hybrid memorycomponent is at maximum storage capacity with required gaming data. Ifit is at maximum storage capacity, the required gaming data is writtenfrom the buffer to a block in the block-addressable memory, wherein therequired gaming data continues to be stored in the buffer during thewriting. If it is not at maximum storage capacity, the buffer continuesto receive required gaming data from the master gaming controller. Ifthe writing operation is complete, at the block-addressable memory, itis checked if the required gaming data has been journaled or storedpersistently. If the required gaming data has been journaledpersistently in the block-addressable memory, a confirmation is sentfrom the block-addressable memory to the byte-addressable memory buffer.The required gaming data is deleted from the buffer when theconfirmation is received. In this manner the buffer is free to receivenew required gaming data, such that required gaming data being writtenis not lost if there is a disruption in the gaming device operationsduring the writing operation. The gaming device is able to storerequired gaming data pursuant to gaming regulations using a combinationof lower-cost non-volatile memory for long-term persistent journalingand higher-cost memory for intermediate buffering of the required gamingdata.

BRIEF DESCRIPTION OF THE DRAWINGS

References are made to the accompanying drawings, which form a part ofthe description and in which are shown, by way of illustration,particular embodiments:

FIG. 1 is an exemplary gaming machine illustrated in perspective view;

FIG. 2 is a partial exemplary architecture for an electronic gamingmachine in accordance with one embodiment;

FIG. 3 is a simplified block diagram of an exemplary gaming machine inaccordance with a specific embodiment of the present invention;

FIG. 4 is a block diagram showing components of a hybrid memorycomponent that may be used in a gaming machine or in othergaming-related components in accordance with one embodiment of thepresent invention;

FIG. 5 is a block diagram showing in greater detail byte-addressablenon-volatile memory and flash memory;

FIG. 6 is a flow diagram of a process of writing data frombyte-addressable non-volatile memory to flash memory in accordance withone embodiment of the spin buffering methods of the present invention;

FIG. 7 is a flow diagram of a process of writing data tobyte-addressable non-volatile memory from other components in the gamingmachine in accordance with one embodiment;

FIG. 8 is a flow diagram of a process of recovering from an incompletewrite operation or any type of error in accordance with one embodiment;and

FIG. 9 is a logical block diagram showing a configuration of a hybridmemory unit in accordance with one embodiment.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Reference will now be made in detail to specific embodiments of theinvention including the best modes contemplated by the inventors forcarrying out the invention. Examples of these specific embodiments areillustrated in the accompanying drawings. While the invention isdescribed in conjunction with these specific embodiments, it will beunderstood that it is not intended to limit the invention to thedescribed embodiments. On the contrary, it is intended to coveralternatives, modifications, and equivalents as may be included withinthe spirit and scope of the invention as defined by the appended claims.In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Thepresent invention may be practiced without some or all of these specificdetails. In addition, well known process operations have not beendescribed in detail in order to not unnecessarily obscure the presentinvention.

Although the present invention is directed primarily to gaming machinesand systems, it is worth noting that some of the apparatuses, systemsand methods disclosed herein might be adaptable for use in other typesof devices or environments, such that their use is not restrictedexclusively to gaming machines and contexts. Such other adaptations maybecome readily apparent upon review of the inventive devices, systemsand methods illustrated and discussed herein. The remainder of thedetailed description herein first provides general discussions of gamingmachines, gaming machine architectures and conventional MRAM devices.Following that, specific embodiments of specialized gaming machineshaving alternative gaming machine architectures are provided, afterwhich various methods of use for such gaming machines and gaming systemsare provided. Finally, exemplary network and system configurations aregiven.

Referring first to FIG. 1, an exemplary gaming machine is illustrated inperspective view. Gaming machine 10 includes a top box 11 and a maincabinet 12, which generally surrounds the machine interior (not shown)and is viewable by users. This top box and/or main cabinet can togetheror separately form an exterior housing adapted to contain a plurality ofinternal gaming machine components therein. Main cabinet 12 includes amain door 20 on the front of the gaming machine, which preferably opensto provide access to the gaming machine interior. Attached to the maindoor are typically one or more player-input switches or buttons 21, oneor more money or credit acceptors, such as a coin acceptor 22 and a billor ticket validator 23, a coin tray 24, and a belly glass 25. Viewablethrough main door 20 is a primary video display monitor 26 and one ormore information panels 27. The primary video display monitor 26 willtypically be a cathode ray tube, high resolution flat-panel LCD,plasma/LED display or other conventional or other type of appropriatevideo monitor. Alternatively, a plurality of gaming reels can be used asa primary gaming machine display in place of display monitor 26, withsuch gaming reels preferably being electronically controlled, as will bereadily appreciated by one skilled in the art.

Top box 11, which typically rests atop of the main cabinet 12, maycontain a ticket printer 28, a key pad 29, one or more additionaldisplays 30, a card reader 31, one or more speakers 32, a top glass 33,one or more cameras 34, and a secondary video display monitor 35, whichcan similarly be a cathode ray tube, a high resolution flat-panel LCD, aplasma/LED display or any other conventional or other type ofappropriate video monitor. Alternatively, secondary display monitor 35might also be foregone in place of other displays, such as gaming reelsor physical dioramas that might include other moving components, suchas, for example, one or more movable dice, a spinning wheel or arotating display. It will be understood that many makes, models, typesand varieties of gaming machines exist, that not every such gamingmachine will include all or any of the foregoing items, and that manygaming machines will include other items not described above.

With respect to the basic gaming abilities provided, it will be readilyunderstood that gaming machine 10 can be adapted for presenting andplaying any of a number of gaming events, particularly games of chanceinvolving a player wager and potential monetary payout, such as, forexample, a wager on a sporting event or general play as a slot machinegame, a keno game, a video poker game, a video blackjack game, and/orany other video table game, among others. While gaming machine 10 cantypically be adapted for live game play with a physically presentplayer, it is also contemplated that such a gaming machine may also beadapted for game play with a player at a remote gaming terminal. Otherfeatures and functions may also be used in association with gamingmachine 10, and it is specifically contemplated that the presentinvention can be used in conjunction with such a gaming machine ordevice that might encompass any or all such additional types of featuresand functions. Gaming machines such as these and other variations andtypes are made by many manufacturers, such as, for example, IGT of Reno,Nev.

With respect to electronic gaming machines in particular, the electronicgaming machines made by IGT are provided with special features andadditional circuitry that differentiate them from general-purposecomputers, such as a laptop or desktop personal computer. Because gamingmachines are highly regulated to ensure fairness, and in many cases areoperable to dispense monetary awards of millions of dollars, hardwareand software architectures that differ significantly from those ofgeneral-purpose computers may be implemented into a typical electronicgaming machine in order to satisfy security concerns and the many strictregulatory requirements that apply to a gaming environment. Descriptionsand examples of current gaming machine architectures can be found in avariety of references, and various discussions of hardware and softwarestructures for an electronic gaming machine are disclosed in, forexample, commonly assigned U.S. Pat. No. 6,804,763 by Stockdale, et al.,entitled “High Performance Battery Backed RAM Interface;” as well ascommonly assigned and co-pending U.S. patent application Ser. No.10/040,239, by LeMay, et al., entitled “Game Development ArchitectureThat Decouples The Game Logic From The Graphics Logic;” and Ser. No.10/041,242, by Breckner, et al., entitled “Decoupling Of The GraphicalPresentation Of A Game From The Presentation Logic,” each of which isincorporated herein in its entirety and for all purposes. A generaldescription of many specializations in electronic gaming machinesrelative to general-purpose computing machines and specific examples ofadditional or different components and features found in such electronicgaming machines now follows.

At first glance, one might think that adapting PC technologies to thegaming industry would be a simple proposition, since both PCs and gamingmachines employ microprocessors that control a variety of devices.However, because of such reasons as 1) the regulatory requirements thatare placed upon gaming machines, 2) the harsh environment in whichgaming machines operate, 3) security requirements and 4) fault tolerancerequirements, adapting PC technologies to a gaming machine can be quitedifficult. Further, techniques and methods for solving a problem in thePC industry, such as device compatibility and connectivity issues, mightnot be adequate in the gaming environment. For instance, a fault or aweakness tolerated in a PC, such as security holes in software orfrequent crashes, may not be tolerated in a gaming machine because in agaming machine these faults can lead to a direct loss of funds from thegaming machine, such as stolen cash or loss of revenue when the gamingmachine is not operating properly.

Accordingly, one difference between gaming machines and common PC basedcomputers or systems is that gaming machines are designed to bestate-based systems. In a state-based system, the system stores andmaintains its current state in a non-volatile memory, such that in theevent of a power failure or other malfunction the gaming machine willreturn to its current state when the power is restored. For instance, ifa player were shown an award for a game of chance and the power failedbefore the award was provided, the gaming machine, upon the restorationof power, would return to the state where the award was indicated. Asanyone who has used a PC knows, PCs are not state machines, and amajority of data is usually lost when a malfunction occurs. This basicrequirement affects the software and hardware design of a gaming machinein many ways.

A second important difference between gaming machines and common PCbased computer systems is that for regulation purposes, the software onthe gaming machine used to generate the game of chance and operate thegaming machine must be designed as static and monolithic to preventcheating by the operator of gaming machine. For instance, one solutionthat has been employed in the gaming industry to prevent cheating andsatisfy regulatory requirements has been to manufacture a gaming machinethat can use a proprietary processor running instructions to generatethe game of chance from an EPROM or other form of non-volatile memory.The coding instructions on the EPROM are static (non-changeable) andmust be approved by a gaming regulator in a particular jurisdiction andinstalled in the presence of a person representing the gamingjurisdiction. Any change to any part of the software required togenerate the game of chance, such as, for example, adding a new devicedriver used by the master gaming controller to operate a device duringgeneration of the game of chance, can require a new EPROM to be burnt,approved by the gaming jurisdiction, and reinstalled on the gamingmachine in the presence of a gaming regulator. Regardless of whether theEPROM solution is used, to gain approval in most gaming jurisdictions, agaming machine must demonstrate sufficient safeguards that prevent anoperator of the gaming machine from manipulating hardware and softwarein a manner that gives the operator an unfair or even illegal advantageover a player. The code validation requirements in the gaming industryaffect both hardware and software designs on gaming machines.

A third important difference between gaming machines and common PC basedcomputer systems is that the number and kinds of peripheral devices usedon a gaming machine are not as great as on PC based computer systems.Traditionally in the gaming industry, gaming machines have beenrelatively simple in the sense that the number of peripheral devices andthe number of functions on the gaming machine have been limited.Further, the functionality of a gaming machine tends to remainrelatively constant once the gaming machine is deployed, in that newperipheral devices and new gaming software is infrequently added to anexisting operational gaming machine. This differs from a PC, where userstend to buy new and different combinations of devices and software fromdifferent manufacturers, and then connect or install these new items toa PC to suit their individual needs. Therefore, the types of devicesconnected to a PC may vary greatly from user to user depending on theirindividual requirements, and may also vary significantly over time for agiven PC.

Although the variety of devices available for a PC may be greater thanon a gaming machine, gaming machines still have unique devicerequirements that differ from a PC, such as device security requirementsnot usually addressed by PCs. For instance, monetary devices such ascoin dispensers, bill validators, ticket printers and computing devicesthat are used to govern the input and output of cash to a gaming machinehave security requirements that are not typically addressed in PCs. ManyPC techniques and methods developed to facilitate device connectivityand device compatibility do not address the emphasis placed on securityin the gaming industry. To address some of these issues, a number ofhardware/software components and architectures are utilized in gamingmachines that are not typically found in general purpose computingdevices, such as PCs. These hardware/software components andarchitectures include, but are not limited to, items such as watchdogtimers, voltage monitoring systems, state-based software architecturesand supporting hardware, specialized communication interfaces, securitymonitoring, and trusted memory.

A watchdog timer is normally used in IGT gaming machines to provide asoftware failure detection mechanism. In a normal operating system, theoperating software periodically accesses control registers in a watchdogtimer subsystem to “re-trigger” the watchdog. Should the operatingsoftware not access the control registers within a preset timeframe, thewatchdog timer will time out and generate a system reset. Typicalwatchdog timer circuits contain a loadable timeout counter register toallow the operating software to set the timeout interval within acertain time range. A differentiating feature of some preferred circuitsis that the operating software cannot completely disable the function ofthe watchdog timer. In other words, the watchdog timer always functionsfrom the time power is applied to the board.

IGT gaming computer platforms preferably use several power supplyvoltages to operate portions of the computer circuitry. These can begenerated in a central power supply or locally on the computer board. Ifany of these voltages falls out of the tolerance limits of the circuitrythey power, unpredictable operation of the computer may result. Thoughmost modern general-purpose computers include voltage monitoringcircuitry, these types of circuits only report voltage status to theoperating software. Out of tolerance voltages can cause softwaremalfunction, creating a potential uncontrolled condition in the gamingcomputer. IGT gaming machines, however, typically have power supplieswith tighter voltage margins than that required by the operatingcircuitry. In addition, the voltage monitoring circuitry implemented inIGT gaming computers typically has two thresholds of control. The firstthreshold generates a software event that can be detected by theoperating software and an error condition generated. This threshold istriggered when a power supply voltage falls out of the tolerance rangeof the power supply, but is still within the operating range of thecircuitry. The second threshold is set when a power supply voltage fallsout of the operating tolerance of the circuitry. In this case, thecircuitry generates a reset, halting operation of the computer.

The standard method of operation for IGT gaming machine game software isto use a state machine. Each function of the game (e.g., bet, play,result) is defined as a state. When a game moves from one state toanother, critical data regarding the game software is stored in a customnon-volatile memory subsystem. In addition, game history or “state”information can include information regarding the amount of credits onthe machine, the state of any game in progress, data regarding previousgames played, amounts wagered, and so forth, any or all of which can bestored in a non-volatile memory device. This feature allows the state ofthe gaming machine to be recovered in the event of a substantialinterruption to the gaming machine, which can include a power outage, agaming machine reset, a critical hardware malfunction, a criticalsoftware malfunction and a gaming machine functional tilt, among otheritems, as will be readily appreciated. This is critical to ensure thatcorrect wagers, credits and other important informational items arepreserved.

Typically, battery backed RAM devices or other similar components areused to preserve this critical data. These memory devices are not usedin typical general-purpose computers. Also, the software structure onthe gaming machine can include a safe storage manager module that isconfigured to update the overall state of the gaming machine to thenon-volatile storage component or components, preferably on a recurringbasis. This safe storage manager can also be configured to restore thegaming machine to a part or all of the overall state stored at anon-volatile storage component. Further details of state based storageand recovery processes in a gaming machine are disclosed in commonlyassigned U.S. Pat. No. 6,804,763, which is again incorporated herein byreference in its entirety and for all purposes.

In addition, substantial interruptions to the gaming machine aretypically monitored for by one or more system managers, such as, forexample, a tilt manager. Machine properties such as power level,temperature, electrostatic level and other factors are monitored, andcautionary signals or tilt generation instructions are sent and actedupon as appropriate when one or more of these properties of the gamingmachine crosses a set tolerance level for whatever reason. Details ofsuch property monitoring and tilt generation processes in a gamingmachine are disclosed in commonly assigned and co-pending U.S. patentapplication Ser. No. 09/954,816, by Breckner, et al., entitled “ModularTilt Handling System,” which is incorporated herein by reference in itsentirety and for all purposes. Continuing further, IGT gaming computersnormally contain additional interfaces, including serial interfaces, toconnect to specific subsystems internal and external to the gamingmachine. The serial devices may have electrical interface requirementsthat differ from the “standard” EIA RS232 serial interfaces provided bygeneral-purpose computers. These interfaces may include EIA RS485, EIARS422, Fiber Optic Serial, optically coupled serial interfaces, currentloop style serial interfaces, and the like. In addition, to conserveserial interfaces internally in the gaming machine, serial devices maybe connected in a shared, daisy-chain fashion where multiple peripheraldevices are connected to a single serial channel.

IGT gaming machines may alternatively be treated as peripheral devicesto a casino communication controller and connected in a shared daisychain fashion to a single serial interface. In both cases, theperipheral devices are preferably assigned device addresses. If so, theserial controller circuitry must implement a method to generate ordetect unique device addresses. General-purpose computer serial portsare not able to do this. In addition, security monitoring circuitsdetect intrusion into an IGT gaming machine by monitoring securityswitches attached to access doors in the gaming machine cabinet.Preferably, access violations result in suspension of game play and cantrigger additional security operations to preserve the current state ofgame play. These circuits also function when power is off by use of abattery backup. In power-off operation, these circuits continue tomonitor the access doors of the gaming machine. When power is restored,the gaming machine can determine whether any security violationsoccurred while power was off, such as by software for reading statusregisters. This can trigger event log entries and further dataauthentication operations by the gaming machine software.

Trusted memory devices are preferably included in an IGT gaming machinecomputer to ensure the authenticity of the software that may be storedon less secure memory subsystems, such as mass storage devices. Trustedmemory devices and controlling circuitry are typically designed to notallow modification of the code and data stored in the memory devicewhile the memory device is installed in the gaming machine. The code anddata stored in these devices may include, for example, authenticationalgorithms, random number generators, authentication keys, operatingsystem kernels, and so forth. The purpose of these trusted memorydevices is to provide gaming regulatory authorities a root trustedauthority within the computing environment of the gaming machine thatcan be tracked and verified as original. This may be accomplished viaremoval of the trusted memory device from the gaming machine computerand verification of the secure memory device contents is a separatethird party verification device. Once the trusted memory device isverified as authentic, and based on the approval of verificationalgorithms contained in the trusted device, the gaming machine isallowed to verify the authenticity of additional code and data that maybe located in the gaming computer assembly, such as code and data storedon hard disk drives.

Mass storage devices used in a general purpose computer typically allowcode and data to be read from and written to the mass storage device. Ina gaming machine environment, modification of the gaming code stored ona mass storage device is strictly controlled and would only be allowedunder specific maintenance type events with electronic and physicalenablers required. Though this level of security could be provided bysoftware, IGT gaming computers that include mass storage devicespreferably include hardware level mass storage data protection circuitrythat operates at the circuit level to monitor attempts to modify data onthe mass storage device and will generate both software and hardwareerror triggers should a data modification be attempted without theproper electronic and physical enablers being present. In addition tothe basic gaming abilities provided, these and other features andfunctions serve to differentiate gaming machines into a special class ofcomputing devices separate and distinct from general purpose computers.

Moving next to FIG. 2, a partial exemplary architecture for theelectronic gaming machine of FIG. 1 is illustrated in block diagramformat. Although it may be appreciated that this architecture resemblesa PC architecture in some ways, there remain various nuances that can bepeculiar to such a gaming machine architecture. It will also beappreciated that the various architectural items illustrated representonly a portion of the many possible architectural elements of a gamingmachine, that many other such items may also be included and/orsubstituted for those shown, and that not every item shown must beincluded. It is also understood that a wide variety of makes and modelsof hardware components can be used for a given item, and that any suchsuitable components are contemplated for use in the present invention.It will be further understood that the various items shown are providedfor purposes of illustration only, need not be in the particularlocations or arrangements shown, much less present at all in a givengaming machine. For example, while primary display 26 is generally at ornear the center of the front face of the gaming machine and speakers arelocated at the gaming machine sides where the top box meets the maincabinet, one or more of these items may be alternatively placed in avariety of other locations or relative arrangements.

As is also shown in FIG. 1, gaming machine 10 generally includes a topbox 11 and main cabinet 12. CPU 50, which is preferably the gamingmachine MGC or a portion thereof, executes the logic provided by gamingsoftware on the gaming machine or system. Such a CPU can be, forexample, a Pentium series processor available from Intel Corporation ofSanta Clara, Calif. or a K6 series processor available from AMDCorporation of Sunnyvale, Calif., among others. To increase theperformance of this MGC or CPU, data and instructions may be stored in amemory cache 51 directly on the CPU 50 or at some other relativelyconvenient location (not shown), such as one that might be locateddirectly off of CPU bus 52, for example. For applications with criticaldata storage requirements, such memory caches are not usually utilizedfor critical data storage, since data stored in these locations may belost in the event of a power failure. Thus, a separate non-volatilememory storage device is utilized, such as NVRAM2 81, as detailedfurther below.

A north bridge 60 is provided essentially as a memory hub adapted tofacilitate and convert communications between various signals, such as,for example, CPU bus signals, Peripheral Component Interface (“PCI”) bussignals, and memory bus signals, among others. One example of suchanother signal can be advanced graphic port (“AGP”) signals, ifapplicable. Signals for the CPU bus 52, PCI bus 69, memory bus 68, AGP(not shown) and others may differ according to the voltage level, clockrate and bit width. Also, the format of appropriate control signals oneach type conduit such as read strobe, write strobe, ready signal fortiming, address signals and data signals may vary from conduit toconduit. North bridge 60, which can be any suitable form of suitablememory hub, such as, for example, an ASIC or Field Programmable GateArray (“FPGA”), among others, enables communications between these andother different types of conduits. For instance, the PCI standard is awell-defined standard used in the personal computer industry, and ismaintained by the Peripheral Component Interface Special Interest Group(“PCISIG”) of Portland, Oreg. PCI version 2.1 typically uses a 66 MHzclock rate and a 32 bit wide data signal at 5 volts to send signals.Other versions of PCI using a 133 MHz clock rate and/or a 64 bit widedata signal may also be available. In contrast, the clock rate used tosend data signals on or “speed” of CPU bus 52 may be much higher, suchas at or above 800 MHz, as will be readily appreciated.

One or more SDRAM units 66 may store various data and items, such as thegaming machine software to be executed by the CPU 50. As is generallyknown, such gaming machine software generally provides and allows a gameto be played on the gaming machine. SDRAM 66 can be in communicationwith the CPU indirectly via north bridge 60, and with the north bridgedirectly via a memory bus 68 or other similar communication link. As isgenerally known in the art, such a memory bus can be relatively fast,operating at a clock rate of at or above 800 MHz, for example. SDRAM 66can be the primary form of storage used by the gaming machine for highspeed data storage and processing during regular gaming machineoperations. It will also be readily appreciated that while SDRAM 66 isrelatively fast, it is generally a volatile form of memory, and as suchmust typically be refreshed or restored upon any new gaming machinepower up or reset, such as by loading software from a more stablesource, such as, for example, a relatively slower hard drive 72 orCD-ROM 73.

North bridge 60 also preferably connects to a wide variety of gamingmachine components, peripherals and additional memory hubs via PCI bus69. Keyboards, printers, audio components, video components, touchscreens, player tracking units, coin acceptors, bill validators, networkcomponents and the like are all examples of devices that may communicatewith CPU 50 via the PCI bus 69. It will be readily appreciated thatwhile several specific examples of PCI bus devices and components areillustrated and discussed as follows, that many more may also be presentand connected to the PCI bus of a gaming machine. As one example, anaudio controller 61, which may send signals to one or more speakers orother sound projection devices, can be connected to PCI bus 69. Videocontroller 62 may also be so connected, and can be used to send signalsto one or more displays connected to the gaming machine, such as primarydisplay 26, such that a game outcome may be presented to a playerplaying a game on the gaming machine. Video controller 62 might beinstalled as part of a video card that includes video memory and aseparate video processor. Using the CPU 50, audio controller 61 andvideo controller 62, high-quality graphics, sound and multimediapresentations may be presented as part of a game play, outcome or otherpresentation.

A tell-tale board 63 adapted to detect and record various events whenthe main power to gaming machine 10 is down or completely off can alsoconnect to PCI bus 69. Such events can be recorded to NVRAM1 67, whichcan be some form of battery backed RAM or flash RAM, for example. Asnoted above, tell-tale board 63 can be battery powered, and in any eventshould at least be adapted to receive power from a source other than themain power source (not shown) of the gaming machine. Such a secondarypower source becomes necessary if the tell-tale board is to perform itsprimary function of recording critical event information while the mainpower is down or off. As also noted above, such recorded events can be,for example, a notice that a main door has been opened, a bill door hasbeen opened, and/or a card cage or “brain box” door has been opened,among others. A network controller 64, which may communicate with one ormore networks including a casino local area network (“LAN”) or a widearea network (“WAN”) can also be connected to PCI bus 69. Such a networkcontroller 64 may allow the gaming machine to communicate with devicesthat provide gaming services, such as an accounting server and a widearea progressive server, among others. The accounting server may pollthe gaming machine for accounting information stored in a non-volatilememory storage device, such as NVRAM2 81. The wide area progressiveserver may receive information stored in NVRAM2 81, such as wagers madeon the gaming machine, and may also send information to be stored in anNVRAM, such as the value of a progressive jackpot.

A generic controller 65 is also shown as being connected to PCI bus 69,with such a controller representing any of the numerous othercontrollers or devices that can also be connected to the PCI bus.Controller 65 could be, for example, a player tracking unit, keyboard,ticket printer, coin acceptor, bill validator, coin hopper or any ofvarious inputs, such as a touch screen or button, for example.

One or more additional information or memory hubs may also be linkedalong PCI bus 69, such as, for example, a south bridge 70. This southbridge 70 may also separately connect to various additional memorydevices, as well as one or more serial ports (not shown), such as thosefor a bill validator. In one particular example, when a monetary bill,printed ticket or other acceptable indicia of credit is accepted by thebill validator, information regarding the denomination of the bill orvalue of the ticket or other indicia may be transferred serially using aNetplex interface to the south bridge 70, with Netplex being an IGTproprietary protocol. Such Netplex serial signals can then be convertedto PCI standard signals by the south bridge 70 using a Netplex devicedriver. Other suitable non-proprietary methods of communication, such asthose under the RS-232 serial standard, may also be used. Theinformation transferred from the bill validator might be treated ascritical game information, whereby non-volatile memory storage such asNVRAM2 81 might be used.

South bridge 70 may contain various components internally, such as ahard drive controller 71, and can be used to connect various stable ROMstorage devices to the system, such as hard drive 72, CD-ROM 73 andEPROM1 74, among others. Some of these devices, such as hard drive 72and CD-ROM 73 can connect to the south bridge 70 via an integrated driveelectronics (“IDE”) bus 75 or other similar connection. As is known inthe art, a typical IDE bus operates at a speed of about 100 MHz, whichis generally appropriate for the access rates of many hard drives andCD-ROM drives. Other devices, such as EPROM1 74, can connect to thesouth bridge 70 via a basic industry standard architecture (“ISA”) bus76, which can be relatively slow in comparison to other buses andconnections. For example, a typical ISA bus might transmit data at aspeed of about 8 MHz, which would be appropriate for an EPROM and othersimilarly slower components. In many gaming machines, the boot programsused in a power up or restart process tend to be in multiple locations,such as an initial basic input/output system (“BIOS”) at a “BOOT 1”location within EPROM1 74 and an extended BIOS at a “BOOT2” locationwithin EPROM2 82, as discussed in greater detail below. Other componentsmight also connect to south bridge 70 by a universal serial bus (“USB”)(not shown) and/or any of a number of other suitable buses andconnections, as will be readily appreciated.

Additional components and storage devices can also be connected to thePCI bus 69 as part of a gaming system extension, such as through an FPGA80 or another similar logic device or memory hub. FPGA 80 can be, forexample, a model XC3S50 FPGA manufactured by Xilinx, Inc. of San Jose,Calif. Alternatively, such a gaming system extension can be another PCIinterface device, such as the PLX 9050 made by PLX Technology ofSunnyvale, Calif. Of course, any other similarly suitable device canalso be used as a gaming system extension. FPGA 80 or other gamingsystem extension can include various serial connections that allowcommunication with several devices, such as player tracking units, widearea progressive systems and casino area networks, among others. Memoryunits that connect to the PCI bus 69 through FPGA 80 or another similarextension can include, for example, a battery backed RAM or othernon-volatile memory unit NVRAM2 81, a boot related memory unit EPROM282, and a “black box” EEPROM 83 for storing data and other gamingmachine specific information, among others. Of course, multiple FPGAs orother similar extension devices may also connect to PCI bus 69, althoughonly one is illustrated here for purposes of simplicity and discussion.

One use for battery backed RAM or otherwise non-volatile NVRAM2 81 is topreserve a game history or state of the gaming machine. Such a gamingmachine history or state can include many details and data itemsregarding information from a game presentation and/or outcome, includingone or more frames from a sequence of frames used in the game outcome orpresentation. Such frames may be copied to NVRAM2 81 from frame buffersresiding on the video controller 62 or at another location in the gamingmachine. As such, NVRAM2 81 is a “safe storage” device for gamingmachine 10, and can be connected to PCI bus 69 for a number of reasons.For one, the PCI bus 69 allows for a relatively fast connection (e.g.,66 or 133 MHz) to the CPU 50 from NVRAM2 81 (via FPGA 80, north bridge60 and the faster CPU bus 52). Such a speedy connection is important,since the software typically does not advance to the next state untilthe current state is executed or rolled back in a state basedtransaction system. Execution of each state involves a number of accessrequests to NVRAM2 81, such that the access rate to this devicetypically affects the performance of the entire gaming machine orsystem. Although a faster connection than PCI bus 69 might be desirable,the speed of this bus tends to be on par with the speed of many typicalbattery backed RAM devices, such that a faster bus would not provide anysignificant advantage when used with NVRAM2 81.

Other reasons for using a PCI bus in association with NVRAM2 81 or otherbattery backed RAM can include the fact that there is typically no datacaching on a PCI bus, which is an important feature where critical datais being backed up, as well as the ability for items on a PCI bus to beinterchangeable and to be tolerant of changes on a main processor board,such as a CPU swap. This permits flexibility in swapping out variousgaming machine components without having to make any correspondingchanges to the NVRAM2 81 for purposes of compatibility. It is preferablethat a gaming machine safe storage component, such as NVRAM2 81, berelatively large, given its critical function of backing up states in agaming machine. Such an inclusion or use of a large non-volatile memoryis usually not a standard component on a PC, thus distinguishing PCsfrom gaming machines at least in this regard. Further details of safestorage at an NVRAM device are disclosed in the previously notedcommonly assigned U.S. Pat. No. 6,804,763 by Stockdale, et al., entitled“High Performance Battery Backed RAM Interface,” which has beenincorporated by reference herein in its entirety and for all purposes.

One use for a one time writable ROM such as EPROM2 82 can be that ofstorage for critical extended BIOS (“BOOT2”), as noted above. In atypical boot up or reset process, the gaming machine is initiallydirected to the initial BIOS program stored at BOOT1 within the EPROM174 connected to south bridge 70. Once this has been booted and actedupon, logic within the BOOT1 direct the gaming machine to the extendedBIOS program stored at BOOT2 within the EPROM2 82 connected to FPGA 80.As will be readily appreciated, both of these processes can involvevarious boot, loading, decryption, authentication and verificationprocesses, and any of a number of suitable encryption techniques may beemployed during these processes. For example, a public-key encryptioncan involve a combination of a private key that is known only to asingle host device and a public-key that is given to any other devicethat wants to communicate securely with the host device. A sendingdevice encrypts a document using the public key from the recipient andits own private key. The receiving device uses the public-key (asprovided by the other device) and its own private key to decode theencrypted message. Files may also be authenticated using digitalsignatures or digital certificates created via the private key of thesender. Such digital certificates permit the recipient to confirm theidentity of the sender, as is generally known in the art.

Uses for a “black box” non-volatile RAM device, such as EEPROM 83, canbe for storing data specific to the exterior cabinet or physicalterminal of a gaming machine or system. Such data can be overall cabinetor terminal based meter data, backup data or code for other gamingmachine or system components, and/or other gaming machine or terminalspecific information, such as country designations, accountingdenominations, machine yield data, progressive jackpot data, volumesettings and overall gaming machine configuration data, among others.The need for such overall EEPROMs or other like storage devicestypically arises due to gaming regulations, gaming operator desire totrack overall data with respect to a machine housing or physicalterminal, or both. As such, this “black box” EEPROM 83 can be located ona back plane board of the gaming machine, such that it remains with theexterior housing when the main processor board or “brain box” and/or itsassociated components are replaced. As is generally known, a “brain box”is typically a sheet metal enclosure within the gaming machine that isadapted to house a number of critical components, such as the MGC orCPU, as well as various memory devices, such as some RAM, NVRAM, thehard drive, and other such components. This brain box can come with alock, and may be removable from the gaming machine as an entire unit insome cases. EEPROM 83 can then be interfaced to the new “brain box”and/or other components that are newly installed, as will be readilyappreciated.

Referring again to FIG. 2, designations for those items that areprimarily associated with the main processor board or “brain box,” suchthat they are typically removed from the gaming machine along with thebrain box when it is replaced, are shown as being within brain boxregion 40. Conversely, those gaming machine items that are primarilyassociated with the gaming machine exterior housing, such that theyremain with the exterior housing while the main processor board isreplaced, are seen as being within back plane board region 41. As shown,replacement of a main processor board typically involves the replacementof CPU 50, its cache 51, north bridge 60, SDRAM 66, south bridge 70,hard drive 72, CD-ROM 73, EPROM1 74, FPGA 80, NVRAM2 81, EPROM2 82 andpossibly one or more other components, such as generic controller 65.Items that usually remain with the cabinet or exterior housing during abrain box swap can include the “black box” EEPROM 83, as well as audiocontroller 61 and speakers 32, video controller 62 and main display 26,tell-tale board 63 and its associated NVRAM1 67, and network controller64, among others.

FIG. 3 is a simplified block diagram of another embodiment of an examplegaming machine 200 in accordance with a specific embodiment of thepresent invention. As illustrated in the embodiment of FIG. 3, gamingmachine 200 includes at least one processor 210, at least one interface206, and memory 216.

In one implementation (not shown), processor 210 and master gamingcontroller 212 are included in a logic device 213 enclosed in a logicdevice housing. In the implementation shown in FIG. 3, processor 210 isin logic device 213 which, together with other components describedbelow, are in master gaming controller 212. Processor 210 may includeany conventional processor or logic device configured to executesoftware allowing various configuration and reconfiguration tasks suchas, for example: a) communicating with a remote source via communicationinterface 206, such as a server that stores authentication informationor games; b) converting signals read by an interface to a formatcorresponding to that used by software or memory in the gaming machine;c) accessing memory to configure or reconfigure game parameters inmemory according to indicia read from the device; d) communicating withinterfaces, various peripheral devices 222 and/or I/O devices 21 1; e)operating peripheral devices 222 such as, for example, card reader 225and paper ticket reader 227; f) operating various 1/0 devices such as,for example, display 235, key pad 230 and a light panel 216; etc. Forinstance, processor 210 may send messages including configuration andreconfiguration information to display 235 to inform casino personnel ofconfiguration progress. As another example, logic device 213 may sendcommands to light panel 237 to display a particular light pattern and tospeaker 239 to project a sound to visually and aurally conveyconfiguration information or progress. Light panel 237 and speaker 239may also be used to communicate with authorized personnel forauthentication and security purposes.

Peripheral devices 222 may include several device interfaces such as,for example: card reader 225, bill validator/paper ticket reader 227,hopper 229, etc. Card reader 225 and bill validator/paper ticket reader227 may each comprise resources for handling and processingconfiguration indicia such as a microcontroller that converts voltagelevels for one or more scanning devices to signals provided to processor210. In one embodiment, application software for interfacing withperipheral devices 222 may store instructions (such as, for example, howto read indicia from a portable device) in a memory device such as, forexample, non-volatile memory, hard drive or a flash memory.

Gaming machine 200 also includes memory 216 which may include, forexample, volatile memory (e.g., RAM 209), non-volatile memory 219 (e.g.,FLASH memory, EPROMs, battery backed RAM, etc.), unalterable memory(e.g., EPROMs 208), alternate storage 217 (e.g., non-volatile memoryimplemented using disk drive(s), flash memory, remote storage, etc.),etc. The memory may be configured or designed to store, for example: 1)configuration software 214 such as all the parameters and settings for agame playable on the gaming machine; 2) associations 218 betweenconfiguration indicia read from a device with one or more parameters andsettings; 3) communication protocols allowing processor 210 tocommunicate with peripheral devices 222 and I/O devices 211; 4) asecondary memory storage device 215 such as a non-volatile memorydevice, configured to store gaming software related information (thegaming software related information and memory may be used to storevarious audio files and games not currently being used and invoked in aconfiguration or reconfiguration); 5) communication transport protocols(such as, for example, TCP/IP, USB, Firewire, IEEE1394, Bluetooth, IEEE802.11x (IEEE 802.11 standards), hiperlan/2, HomeRF, etc.) for allowingthe gaming machine to communicate with local and non-local devices usingsuch protocols; etc. Typically, the master gaming controller 212communicates using a serial communication protocol. A few examples ofserial communication protocols that may be used to communicate with themaster gaming controller include but are not limited to USB, RS-232 andNetplex (a proprietary protocol developed by IGT, Reno, Nev.).

A plurality of device drivers 242 may be stored in memory 216 orseparately as shown. Example of different types of device drivers mayinclude device drivers for gaming machine components, device drivers forperipheral components 222, etc. Typically, device drivers 242 utilize acommunication protocol of some type that enables communication with aparticular physical device. The device driver abstracts the hardwareimplementation of a device. For example, a device driver may be writtenfor each type of card reader that may be potentially connected to thegaming machine. Examples of communication protocols used to implementdevice drivers 259 include Netplex 260, USB 265, Serial 270, Ethernet275, Firewire 285, I/O debouncer 290, direct memory map, serial, PCI 280or parallel. Netplex is a proprietary IGT standard while the others areopen standards. According to a specific embodiment, when one type of aparticular device is exchanged for another type of the particulardevice, a new device driver may be loaded from memory 216 by processor210 to allow communication with the device. For instance, one type ofcard reader in gaming machine 200 may be replaced with a second type ofcard reader where device drivers for both card readers are stored in thememory 216.

In some embodiments, gaming machine 200 may also include variousauthentication and/or validation components 244 which may be used forauthenticating/validating specified gaming machine components such as,for example, hardware components, software components, firmwarecomponents, information stored in the gaming machine memory 216, etc.

In some embodiments, the software units stored in the memory 216 may beupgraded as needed. For instance, when the memory 216 is a hard drive,new games, game options, various new parameters, new settings forexisting parameters, new settings for new parameters, device drivers,and new communication protocols may be uploaded to the memory from themaster gaming controller 104 or from some other external device. Asanother example, when the memory 216 includes a CD/DVD drive including aCD/DVD designed or configured to store game options, parameters, andsettings, the software stored in the memory may be upgraded by replacinga first CD/DVD with a second CD/DVD. In yet another example, when thememory 216 uses one or more flash memory 219 or EPROM 208 units designedor configured to store games, game options, parameters, settings, thesoftware stored in the flash and/or EPROM memory units may be upgradedby replacing one or more memory units with new memory units whichinclude the upgraded software. In another embodiment, one or more of thememory devices, such as the hard-drive, may be employed in a gamesoftware download process from a remote software server.

FIG. 4 is a block diagram showing components of a hybrid memorycomponent that may be used in a gaming machine or in gaming-relatedcomponents, such as accounting systems and player tracking systems, inaccordance with one embodiment of the present invention. Various typesof gaming data, described in greater detail below, are received from amaster gaming controller (or CPU) 402 or other appropriate component ina gaming machine at a non-volatile memory manager 404 which may beimplemented as a hardware component or as a software module. Thus, box404 may represent a hardware or software component or a combination ofboth. In other embodiments, memory manager 404 may not be required. Forexample, a more generic data logger component or any component suitable,such as those described above, for managing the writing of all types ofgame-related data to the non-volatile memory may be used.

A non-volatile memory component 406 may consist of at least twocomponents: a byte-addressable non-volatile memory 408 and ablock-addressable non-volatile memory 410. For ease of illustration anddiscussion, block-addressable non-volatile memory 410 may be referred toas “flash memory” or “flash,” in specific embodiments (and may be adifferent component from the flash memories described above). Forexample, it may be implemented as a flash chip or as a compact flashcard, although it is understood that other suitable types of memorydevices may be used in place of flash memory, such as hard disks, asdiscussed below. Thus, flash memory is used in but one embodiment of thehybrid memory and spin buffering techniques of the present invention.

FIG. 5 is a block diagram showing in greater detail byte-addressablenon-volatile memory 408 and flash memory 410. In one embodiment,byte-addressable non-volatile memory 408 has a series of three or morebuffers. The number of buffers needed may depend on the volume of databeing sent from the gaming machine components and the manner in whichsuch data is received (e.g., the frequency of “data bursts” from thegaming machine). In one embodiment, a buffer can store 512 bytes. Thecapacity of a buffer A 502, for example, may depend directly on the sizeof the block or sectors in flash memory 410 (e.g., 512k, 1024k, 4096k,etc.). Details on deriving the adequate or appropriate size of a bufferto meet the gaming system's needs and the jurisdictional requirementsare described below. Also stored in byte-addressable non-volatile memory408 are “housekeeping” or administrative data 504. In an alternativeembodiment, non-volatile memory 408 may have management firmware. In theprimary embodiment, the operations of byte-addressable non-volatilememory 408 and flash memory 410 (described below) are managed by memorymanager 404.

Flash memory 410 may consist of multiple blocks, such as Block A 508,which in one embodiment has a capacity of 512 bytes. As described below,in other embodiments, the size of a memory block in flash 410 may vary,but is typically a multiple of the sector size. In other embodiments, ahard disc or other rotating platter-type memory device may be used.

FIG. 5 also shows exchange of data from memory 408 to 410 andconfirmations from memory 410 to memory manager 404 or directly tobyte-addressable memory 408, which are described in the flow diagramsbelow. In brief, gaming data is written to block-addressablenon-volatile memory 410 for persistent storage and confirmations aresent from it to byte-addressable non-volatile memory 408 at specificstages in the operation.

FIG. 6 is a flow diagram of a process of writing data frombyte-addressable non-volatile memory to flash memory in accordance withone embodiment of the spin buffering methods of the present invention.It will be understood that not every step provided for is necessary,that other steps might be included, such as start or reboot processes,and that the order of steps might be rearranged as desired for a givenapplication. At step 602 non-volatile memory manager 404 determineswhether a buffer in byte-addressable non-volatile memory is in a FULLstate by checking housekeeping data. If the buffer is full, the state ofthe buffer is changed to BUSY (or something similar) in preparation ofthe writing operation of the data to flash memory (or block-addressablenon-volatile memory). At step 606 the data in it is written to a blockin block-addressable non-volatile memory. If at step 602 it isdetermined that the buffer is not FULL, data is continued to be writtento the buffer at step 603. In one embodiment at step 602, thenon-volatile memory manager 404 continues to check the buffer until thebuffer is in a FULL state.

At step 608 memory manager 404 or a logic component in byte-addressablenon-volatile memory 406 determines whether the write operation iscomplete, for example, by checking the contents of the buffer. If thebuffer write operation is not complete, the memory manager continueschecking. If it is determined that the write operation is complete, theblock-addressable non-volatile memory checks whether the data has beenstored persistently or made permanent in the flash memory at step 609.If it has not, given that writing is complete, flash memory continues tocheck whether the data is stored safely. If it has, at step 610block-addressable memory 410 transmits a confirmation to thebyte-addressable buffer or, more generally, sends a confirmation to thenon-volatile memory manager 404.

As noted above, if there is a power failure or other disruption duringthe write operation, none of the data is lost because of thecharacteristics of byte-addressable non-volatile memory 408 which willcontinue to store the data that is being written in case of an abnormalevent. In other words, the data remains persistent in the buffer untilthere is a confirmation. In contrast, data in the block may be lost ifthere is a disruption during the write operation. By sending aconfirmation (i.e., data received and persistently stored) tonon-volatile memory manager 404, the flash memory is essentiallyinforming byte-addressable non-volatile memory 408 that it is now safeto erase the data and mark the buffer as FREE. Thus, at step 612, thebuffer is placed in the FREE state and a block index or pointer isincremented so that non-volatile memory 408 will write to a free blockin the next write operation. At this stage the process returns tochecking if a buffer is full at step 602.

FIG. 7 is a flow diagram of a process of writing data tobyte-addressable non-volatile memory from other components in the gamingmachine in accordance with one embodiment. At step 702 non-volatilememory manager 404 or other component in the byte-addressablenon-volatile memory 408 reads housekeeping or administrative data forthe memory in order to select the next free buffer for receiving data.At step 704 the state of the selected buffer is BUSY or equivalentindicating that it is storing data and no longer free. At step 705incoming game data is written to the selected buffer. As described ingreater detail below, game data is intended to encompass a broad rangeof types and categories of data, including game state and machine eventdata, such as actions that occur asynchronously, including buttonpushes, door opens, bonus events, and the like, among many others.

At step 706 memory manager 404 determines whether the buffer has reachedcapacity, the size of which may vary in different embodiments. If thebuffer is not full, the writing or storing process continues at step705. If the buffer is full, the state of the buffer is changed to FULLor unavailable at step 708 and the process is complete.

FIG. 8 is a flow diagram of a process of recovering from an incompletewrite operation or any type of error in accordance with one embodiment.This process takes place before any normal operations (or before anyatypical operations) are allowed to proceed on the gaming machine. Itmay be run at boot up or start up of the gaming machine after a powerfailure, tilt, or any other unexpected interruption in the gamingmachine operations that may effect the writing of data frombyte-addressable non-volatile memory to flash memory 410 and thereby mayviolate the integrity of data that, by gaming regulation and/or casinopolicy, is required to be stored.

At step 802 the appropriate component, such as the non-volatile memorymanager 404 or master gaming controller 402 determines whether there wasa write operation between a byte-addressable buffer and a block in flashmemory when the failure occurred. This may be done by checking a statevariable of the buffers. The byte-addressable non-volatile memoryhousekeeping data may also have a block address as well. In oneembodiment, the byte-addressable memory housekeeping data or similardata may indicate that “This is where each buffer was at the moment offailure and this is what each buffer was doing (i.e., it was empty,being written to, or being read from) when the failure occurred.”

If there was a write operation in progress, then in one embodiment,portions of data that were written to the block are erased from flashmemory. If a hard disc is being used to log the data, the erasing stepmay not be necessary. Housekeeping data in flash or byte-addressablememory may have data indicating which portions or sectors of flashshould be erased. At step 806 the data from the buffer, which isunaffected from the failure, is re-written to the block in flash memory.This process is generally the same as the process described above inFIGS. 6 and 7. In one embodiment, the data is written to the same blockin flash that was being used before the power failure or disruption.Housekeeping data may be used to re-initiate the data writing processfrom the buffer to the block. As noted above, data in thebyte-addressable non-volatile memory buffer is not lost. After the writeoperation is completed and confirmation from flash memory is received,the buffer is marked as FREE so that it may begin storing new data atstep 808 at which stage the process is complete.

FIG. 9 is a logical block diagram showing a configuration of a hybridmemory unit that may be used to implement one embodiment. A memory chip902 has a byte-addressable non-volatile memory component 904 that maybe, for example, a non-volatile RAM, such as CMOS, MRAM, PRAM, and othermemory types known to those skilled in the art that will continue tostore data in the absence of electrical power. Some of these may bebattery backed, such as CMOS nvRAM. Also contained in memory chip 902 isa block-addressable memory 906 or, what has been referred to herein as,flash memory. One suitable type of flash memory is single-level per cellNAND-FLASH. For example, a Compact FLASH Card (CF-Card) may be used. Thetwo memory components 904 and 906 are in communication with each othervia an FPGA component 908, one implementation of non-volatile memorymanager 404 that enables data transfer between the two memorycomponents, maintains housekeeping data, and communicates with othercomponents in the gaming machine. In this manner, the hybrid memory andspin buffering technique of the present invention may be modularized ina single memory single integrated circuit or a component comprisingmultiple integrated circuits that can be removed from a gaming machineor, conversely, kept in a gaming machine while other components, such asthose on or off the main processor board are removed. Of course, otherembodiments implementing the hybrid memory may be used in a gamingmachine and FIG. 9 shows only one example. For example, a hybrid memoryof the present invention may be implemented as a plug-in card or chip.

As described above, one reason the hybrid memory of the presentinvention is beneficial is because data that is required to be stored(as dictated by gaming regulations) is not lost during a powerinterruption, during a write operation, or lost due to flash sectordamage, if flash memory is used as one component in the hybrid memory.In various embodiments, a buffer in the byte-addressable non-volatilememory 408 is 512 bytes, 1024 bytes, 2048 (2k) bytes, or 4096 (4k)bytes.

Sufficient capacity is needed to satisfy potential, however unlikely,gaming situations and maintain adherence with gaming control boardregulations. For example, a gaming jurisdiction may require thattransactional data on 100 games, each having a possible 100 secondarygames, be stored and accessible at all times. Thus, storage capacity forgaming data for 10,000 games should be available, even if the likelihoodthat all of it will be needed is small.

In one embodiment, the byte-addressable non-volatile memory, forexample, Freescale's magnetoresistive RAM (MRAM), does not require abattery. In another embodiment, it may be a battery-backed CMOS-SRAM oran nvRAM from Simtek. In another embodiment, it may be a phase-changeRAM or PRAM.

In one embodiment, the byte-addressable and the block-addressablenon-volatile memories are on a main processor board, along with themaster gaming controller board in the gaming machine. In anotherembodiment, it is on a compact flash card with its own controller, forexample implemented as an FPGA as shown in FIG. 9 (and shown in FIG. 2).In another embodiment, a portion of the block-addressable memory may bea hard drive, on a server in the gaming network, or on the Internet.

As noted above, a buffer (also referred to in the art as “heaps”) in thebyte-addressable non-volatile memory has a state. In one embodiment,these states include FREE, BUSY, FULL, and WRITE. In other embodiments,there may be more states. With respect to buffer size, the size of thebuffer may depend on several factors. These include size of a block orsector in flash memory, the amount of data generated, and other relevantfactors, discussed in greater detail below.

When a buffer reaches full capacity, non-volatile memory managersoftware 404 may request a next free buffer in the buffer chain. In oneembodiment, a pointer is moved to point to the next available buffer.Concurrently, another buffer may be writing to a block in flash memory,thereby placing the buffer in a WRITE state. When it has finished, thestate of the buffer is changed to FREE.

If there is a need to burst a large volume of data within the gamingmachine, it is preferable to have more than three buffers (e.g., buffers502) in the byte-addressable non-volatile memory. Large bursts of datamay occur in the gaming machine context under circumstances such as whena data packet is transmitted or “pumped” for each synchronous orasynchronous event. In one scenario, a tilt may cause another tilt untilthe machine stops operating, triggering a multitude of asynchronousevents each represented by one or more data packets, which may begreater than 512 bytes. In one embodiment, the size of the buffer is inaccord with the granularity of the block size in the block-addressablenon-volatile memory device. For example, a flash memory block size maybe 512 bytes, 1024 bytes or 2048 bytes for some flash devices. Somehigher density flash devices may have 16k block sizes. In oneembodiment, an entire write operation (from byte-addressable memory toblock-addressable memory) is performed in one operation to the blockdevice.

In one embodiment, the flash memory or, more broadly, theblock-addressable memory, and the byte-addressable memory are kept inthe cabinet of the gaming machine while other components of the gamingmachine are changed. They may also be kept in other areas of a gamingmachine (described in more detail in FIGS. 1 and 2). It is preferablethat they be kept together in the event there is a power off during datatransfer and the transfer is not complete. For example, thebyte-addressable and block-addressable memories can be kept on the mainprocessing board (or on a separate board that is permanently attached tothe machine) as a pair, so even if components such as the electronics,slot tray, and the like are changed or replace, then the memory pair maystay with the machine.

One use for non-volatile memory is to preserve a game history or stateof the gaming machine. Such a gaming machine history or state caninclude many details and data items regarding information from a gamepresentation and/or outcome, including one or more frames from asequence of frames used in the game outcome or presentation. Such framesmay be copied to non-volatile memory from frame buffers residing onvideo controller 62 or at another location in the gaming machine.

Non-volatile memory plays a significant role in the normal operation ofa gaming machine. It may store data classified as permanent or temporarydata. The permanent type of data is described herein as critical data.Critical data comprises data considered to be highly important andrelates to the current or previous state(s) of a gaming machine.Examples of critical data include game history information, securityinformation, accounting information, player tracking information, widearea progressive information, game state information, game usageinformation, game transactional information, game meter information,bonus of game information, player input information, and licenseinformation. Some of these types of data are described in greater detailbelow, or any “critical” game related data. Critical data such as theamount of funds credited to or paid out from a gaming machine may bestored permanently in non-volatile memory as accounting information.This critical accounting information would reflect its current and priorstates over successive rounds of play.

Among the types of commonly preserved data is so-called “critical data”or “critical game information,” which must be maintained by casinos orother gaming machine establishment. Such data may be stored as simpletext and/or graphics. In some cases, entire frames of video data may becaptured for this purpose.

Examples of critical game transactions include, but are not limited to,reading credit information from a debit card, adding an amount of creditto a gaming machine, and accepting currency from a player. The criticalgame transaction may require the use of non-volatile memory eithertemporarily or more permanently. The non-volatile memory may storevalues temporarily as an intermediate step in the calculation ofcritical data. For example, when accepting currency from a player, abill validator may determine the value of the currency as an integernumber of dollars. This information may be stored into non-volatilememory temporarily, as an intermediate operational step, prior todetermining the number of credits credited in the gaming machine. If thegame comprises a 25 cent game, the number of credits calculated wouldcorrespond to forty credits if the player inserts a ten dollar bill. Inthis example, the critical data stored permanently in non-volatilememory may comprise the number of credits (forty), although the numberof dollars (ten) would comprise an intermediate operational value in thecalculation of the number of credits. As a consequence, the intermediatevalue ten may comprise data that is stored temporarily in non-volatilememory and is deleted upon the calculation of the critical data valueforty which may be stored permanently in non-volatile memory.

Game history information may provide a record of outcomes for a numberof rounds of play for a game in a gaming machine. For example, gamehistory information may be used to verify the payouts of a gamingmachine so that a verification of a winning jackpot may be performedbefore a payout is made if suspicious activity is recognized. Gamehistory may also be used, for example, to audit the types of jackpotsgenerated over a specified number of rounds of play or to provideevidence that a gaming machine has been tampered with. Hence, this typeof information is critical to the casino or gaming machine owner.

Information that provides a running count or history of the credits thatgo in and out of the gaming machine may provide valuable accountinginformation. For example, a gaming machine's cumulative number ofcredits may be based on the bills or coins collected, the amount ofcredits generated from the insertion of a credit card, or bonus creditscreated by inputting a PIN (personal identification number). This typeof data may be very useful to a gaming operator because it provides therevenue a gaming machine generates over a period of time.

Security information may provide information related to a tamperingevent on the gaming machine. Details of this information may includetime of day, type of game, the amount wagered, the specific outcome, andany operational information, such as diagnostics related to thecondition of the gaming machine when tampering occurred.

Player tracking information is also vital to providing valuable feedbackregarding a player's preferences. A casino may track player informationto provide the best and most desirable playing environment to theplayer. Whether it be type of game, denomination of game, length ofplay, amount played, or the like, these factors provide usefulinformation to the gaming operator it can better attract and maintaingame play from a player.

A few specific examples of critical data may include, for example, oneor more of the following: (1) Main door/Drop door/Cash door openings andclosings, (2) Bill insert message with the denomination of the bill, (3)Hopper tilt, (4) Bill jam, (5) Reel tilt, (6) Coin in and Coin outtilts, (7) Power loss, (8) Card insert, (9) Card removal, (10) Jackpot,(11) Abandoned card (12) querying the non-volatile memory for thecurrent credit available on the gaming machine, (13) reading the creditinformation from a player's card, (14) adding an amount of credits tothe gaming machine, (15) writing to a player's card via the card readerand the device drivers to deduct the amount added to gaming machine fromthe card, and (16) copying the new credit information to thenon-volatile memory. Such information may be required, based onjurisdictional gaming regulations, to be stored for a certain period oftime, e.g., 75 game plays after the information was accumulated.

As described above, non-volatile memory may be configured or designed tomaintain the contents of its memory over time through the use of abattery as a power source, thereby allowing it to be independent ofexternally supplied power. As a result, non-volatile memory can continueto store data such as accumulated information as long as power issupplied.

The accumulative data to be saved may take the form of text, graphics,frames, video clips, etc. In the simplest case, it is merely textualdata describing a game's state, history, statistics, etc. A morememory-intensive form of data storage stores frames (essentially bitmaps of video still shots) for selected portions of the gamepresentation; e.g., frames associated with user inputs and presentationof game outcomes. Some of these frames may have embedded or associateddata providing specific details such as state, statistics, etc. asdescribed above. Yet another way to save relevant game play informationis via a game play sequence that represents the game as it appearedoriginally. This involves presentation of a series of frames andassociated events, including, for example, user interactive events. Suchmay be implemented using a series of critical or desired snapshotsand/or screenshots, a movie or video clips of a game play, and/or othermechanisms representing the game play information. To implement thistype of replay, it may be desirable to preserve essential stateinformation about the game and then re-execute the game code using suchstate information.

During the course of game play, a gaming machine may undergo a number ofdifferent events, such as receiving currency, hopper tilt, reel tilt,protective tilt, power loss, player's card input, player's card removal,personal identification input, reel spin, multi-denomination change,jackpot tilt, and the like. During these transactional events, thetemporary or permanent non-volatile memory or non-volatile storagerequirements of the game or the gaming machine may change. Accordingly,memory space allocations are continuously monitored.

Gaming regulators, such as the Nevada gaming commission, require thatgaming machines prohibit the writing of code, data and/or other gaminginformation to gaming machine disk drives by sources other than trustedmemory sources which have been properly verified and authenticated.Because of such regulatory constraints, it has been conventionalpractice in the gaming industry to design and implement mechanisms forpreserving critical data in the gaming machine's non-volatile memorywithout utilizing memory storage at the gaming machine's disk drive(s).

While the invention has been particularly shown and described withreference to specific embodiments thereof, it will be understood bythose skilled in the art that changes in the form and details of thedisclosed embodiments may be made without departing from the spirit orscope of the invention. However, it will be understood that embodimentsin which such games are developed without such templates are within thescope of the invention. In addition, the host of a game developmentenvironment implemented according to the present invention does notnecessarily need to be a gaming machine provider or manufacturer toremain within the scope of the invention. And as discussed above, any ofa wide range of technologies may be employed to implement and provideaccess to such a game development environment.

Finally, although various advantages, aspects, and objects of thepresent invention have been discussed herein with reference to variousembodiments, it will be understood that the scope of the inventionshould not be limited by reference to such advantages, aspects, andobjects. Rather, the scope of the invention should be determined withreference to the appended claims.

1. A gaming machine comprising: at least one processor; at least oneinterface; a hybrid non-volatile memory component having abyte-addressable non-volatile memory sub-component and ablock-addressable non-volatile memory sub-component, thebyte-addressable sub-component having at least three buffers and theblock-addressable sub-component having at least one block, whereincritical gaming data is transferred from the byte-addressablesub-component to the block-addressable sub-component, where it ispermanently stored; and wherein a confirmation is sent from theblock-addressable sub-component to the byte-addressable sub-componentwhen the critical gaming data is permanently stored; and wherein thecritical gaming data is deleted from the byte-addressable sub-componentwhen the confirmation is received.
 2. A gaming machine as recited inclaim 1 further comprising: a hybrid non-volatile memory manager forcontrolling operations of the hybrid non-volatile memory component.
 3. Agaming machine as recited in claim 1 wherein the block-addressablesub-component is a flash memory.
 4. A gaming machine as recited in claim1 wherein the size of a buffer in the byte-addressable sub-componentdepends on the size of a block in block-addressable sub-component.
 5. Agaming machine as recited in claim 1 wherein critical gaming data isselected from the group consisting of game history information, securityinformation, accounting information, player tracking information, widearea progressive information, game state information, game usageinformation, game transactional information, game meter information,bonus of game information, and player input information.
 6. A gamingmachine as recited in claim 1 wherein the hybrid non-volatile memorymanager is an FPGA.
 7. A gaming machine as recited in claim 6 whereinthe hybrid non-volatile memory component and the memory manager are onthe same chip in the gaming machine.
 8. A gaming machine as recited inclaim 7 wherein the chip is on a main processing board of the gamingmachine.
 9. A gaming machine as recited in claim 1 wherein the criticalgaming data is transmitted to the hybrid non-volatile memory componentfrom the at least one processor.
 10. A method of storing gaming data ina hybrid memory component in a gaming machine, the gaming data requiredto be stored by a gaming operator pursuant to gaming regulations, themethod comprising: receiving gaming data at the hybrid memory componentfrom one or more components in the gaming machine; determining if abyte-addressable non-volatile memory buffer in the hybrid memorycomponent is at maximum storage capacity with gaming data; if it is atmaximum storage capacity, writing the gaming data from the buffer to ablock in the block-addressable non-volatile memory, wherein the gamingdata continues to be stored in the buffer during the writing; if it isnot at maximum storage capacity, continuing to receive gaming data fromthe one or more components; if the writing operation is complete, at theblock-addressable non-volatile memory, checking if the gaming data hasbeen stored persistently; is if the gaming data has been storedpersistently in the block-addressable non-volatile memory, sending aconfirmation from the block-addressable non-volatile memory to thebyte-addressable non-volatile memory buffer; and deleting the gamingdata from the buffer when the confirmation is received, thereby freeingthe buffer to receive new data, such that gaming data is not lost ifthere is a disruption during the writing operation.
 11. A method asrecited in claim 10 further comprising checking the contents of thebuffer to determine if the buffer is at maximum storage capacity.
 12. Amethod as recited in claim 10 further comprising sending theconfirmation to a non-volatile memory manager, wherein the non-volatilememory manager is a component in the hybrid memory component of thegaming machine.
 13. A method as recited in claim 10 further comprising:reading byte-addressable non-volatile memory administrative data todetermine a next available buffer for receiving gaming data; andchanging a state of the buffer to indicate it is receiving gaming data.14. A method as recited in claim 10 further comprising: determining ifthe writing operation of gaming data from the buffer to the block iscomplete; and if complete, changing a state of the buffer to indicatethat it is at maximum storage capacity.
 15. A method as recited in claim10 further comprising: determining if the writing operation was inprogress between a byte-addressable buffer and the block inblock-addressable non-volatile memory during a disruption in the gamingmachine operations; if gaming data was being written to the block duringthe disruption, erasing the data from the block upon resumption ofgaming machine operations; and re-writing the gaming data from thebyte-addressable buffer to the block.
 16. A method as recited in claim15 further comprising: reading administrative data in thebyte-addressable non-volatile memory to determine which sectors in theblock should be erased.
 17. A method as recited in claim 15 furthercomprising checking a state variable of the block-addressable buffer.18. A method as recited in claim 10 wherein the gaming data is selectedfrom the group consisting of game history information, securityinformation, accounting information, player tracking information, widearea progressive information and game state information, game usageinformation, game transactional information, game meter information,bonus of game information, and player input information.
 19. A gamingdevice capable of storing required gaming data pursuant to wager gamingregulations comprising: a master gaming controller; a hybridnon-volatile memory component having a byte-addressable memory, ablock-addressable memory, and an FPGA; and a memory storing computerinstructions for: receiving the required gaming data at the hybridmemory component from the master gaming controller; determining if abyte-addressable non-volatile memory buffer in the hybrid memorycomponent is at maximum storage capacity with required gaming data; ifit is at maximum storage capacity, writing the required gaming data fromthe buffer to a block in the block-addressable memory, wherein therequired gaming data continues to be stored in the buffer during thewriting; if it is not at maximum storage capacity, continuing to receiverequired gaming data from the master gaming controller; if the writingoperation is complete, at the block-addressable memory, checking if therequired gaming data has been journaled persistently; if the requiredgaming data has been journaled persistently in the block-addressablememory, sending a confirmation from the block-addressable memory to thebyte-addressable memory buffer; and deleting the required gaming datafrom the buffer when the confirmation is received, thereby freeing thebuffer to receive new required gaming data, such that required gamingdata being written is not lost if there is a disruption in the gamingdevice operations during the writing operation, and wherein the gamingdevice is able to store required gaming data pursuant to gamingregulations using a combination of lower-cost non-volatile memory forlong-term persistent journaling and higher-cost memory for intermediatebuffering of the required gaming data.
 20. A gaming device as recited inclaim 19 wherein the memory further comprises computer code for:determining if the writing operation of required gaming data from thebuffer to the block is complete; and if complete, changing a state ofthe buffer to indicate that it is at maximum storage capacity.
 21. Agaming device as recited in claim 19 wherein the memory furthercomprises computer code for: determining if the writing operation was inprogress between a byte-addressable buffer and the block inblock-addressable memory during a disruption in the gaming machineoperations; if the required gaming data was being written to the blockduring the disruption, erasing the required data from the block uponresumption of gaming machine operations; and re-writing the requiredgaming data from the byte-addressable buffer to the block.
 22. A gamingdevice as recited in claim 19 wherein the required gaming data isselected from the group consisting of game history information, securityinformation, accounting information, player tracking information, widearea progressive information, game state information, game usageinformation, game transactional information, game meter information,bonus of game information, and player input information.